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Body Effect

Sini Mukundan    February 11, 2019 February 8, 2019    No Comments on Body Effect

1. Threshold Voltage Body effect refers to the change in the threshold voltage of the device when there is a difference between substrate(body) and source voltages. Body bias is usually… Read more »

Back End, Physical Design    threshold voltage
CMOS cross section with well ties

Threshold Voltage

Sini Mukundan    February 8, 2019 February 11, 2019    No Comments on Threshold Voltage

To discuss the svt, hvt and lvt cells used for power aware designing, we need to first iterate our understanding of threshold voltage. Let’s consider the NMOS in the above… Read more »

Back End, Physical Design    hvt, lvt, svt, threshold voltage

TCL Training Series – Passing an array as procedure argument

Sini Mukundan    February 7, 2019 February 7, 2019    1 Comment on TCL Training Series – Passing an array as procedure argument

A TCL array is an associative array. i.e. there is an (un-ordered) key-value pair in a TCL array. A simple list of elements as in a perl array or a… Read more »

General, TCL Programming    TCL

Clock Groups : set_clock_groups

Sini Mukundan    February 6, 2019 February 7, 2019    No Comments on Clock Groups : set_clock_groups

Back when I gave an introduction to SDC, I brushed upon set_false_path statements between clocks. However, now there is a more efficient way of specifying the the clock exceptions in… Read more »

Back End, Physical Design, STA    asynchronous, false paths, logically_exclusive, physically_exclusive, sdc, set_clock_groups

Two Stage Synchonizers

Sini Mukundan    February 5, 2019 February 5, 2019    No Comments on Two Stage Synchonizers

When an asynchronous signal, or a signal from a block clocked by a different clock is received by a synchronous circuit, it is imperative that it is reliably sampled by… Read more »

Back End, Physical Design, STA    mtbf

Metastability

Sini Mukundan    January 29, 2019 January 29, 2019    No Comments on Metastability

In digital circuit, the signal is required to be within certain voltage or current limits (logic 0/1 levels) for correct circuit operation. If the signal is within an intermediate range… Read more »

Back End, STA    mtbf, reliability

TCL Training Series – upvar

Sini Mukundan    January 10, 2019 January 10, 2019    3 Comments on TCL Training Series – upvar

We have seen the command “uplevel” and how to use it earlier. Now, let’s look into a related command upvar. Syntax The TCL language reference manual gives the following description… Read more »

General, TCL Programming    TCL

TCL Training Series – uplevel

Sini Mukundan    December 18, 2018 December 18, 2018    No Comments on TCL Training Series – uplevel

uplevel is a built-in tcl command that evaluates a script in a different level. Syntax uplevel ?level? arg ?arg …? level here can be number or a # followed by… Read more »

Scripts, TCL Programming    TCL
Common Path Pessimism Removal

Common Path & Clock Reconvergence Pessimism Removal

Sini Mukundan    May 10, 2018 May 10, 2018    4 Comments on Common Path & Clock Reconvergence Pessimism Removal

Many a time your chip is overdesigned due to undue pessimism in timing calculations. Pessimism in timing analysis makes it difficult for designs to close timing and it is imperative… Read more »

Back End, Physical Design, STA    clock reconvergence pessimism, common path pessimism removal, cppr, sta, timing
Skewed clock to fix timing violation

Useful Skew

Sini Mukundan    May 8, 2018 May 8, 2018    2 Comments on Useful Skew

For clock trees, the traditional way is to go with zero skew or balanced skew. For each of the sinks, the insertion delay is kept to be equal so that… Read more »

Back End, Physical Design    cts, optimization, skew, useful skew

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System Verilog

  • SV Event Scheduling Algorithm
  • System Verilog: Dynamic Arrays
  • System Verilog: Associative Arrays
  • System Verilog : Queues
  • System Verilog : Array querying system functions
  • System Verilog : Array Reduction & Array Ordering Methods
  • System Verilog : Mailbox
  • System Verilog : Fork Join
  • System Verilog : Disable Fork & Wait Fork
  • System Verilog : Rand & Randc
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SVA Properties

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  • SVA Properties II : Types
  • SVA Properties III : Implication
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