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ASIC Physical Design Flow

Sini Mukundan    June 6, 2019 June 6, 2019    No Comments on ASIC Physical Design Flow

In the VLSI design cycle, after the circuit representation is complete, we go to “physical design”. This is the stage where the circuit description is transformed into a physical layout,… Read more »

General    physical design flow

Multicycle paths between different clock domains

Sini Mukundan    May 22, 2019 May 22, 2019    No Comments on Multicycle paths between different clock domains

We have seen set_multicycle_path constraint for timing path within a single clock domain. Now let’s explore multicycle paths with two synchronous clock domains of different frequencies. The SDC command `set_multicycle_path`… Read more »

Physical Design, STA    sdc, timing

Peak and Average Power

Sini Mukundan    March 29, 2019 March 29, 2019    No Comments on Peak and Average Power

If you were to measure the power dissipated by a chip over a time period, the dissipated power vary at each instant of time. Peak power refers to the maximum… Read more »

Back End, Physical Design    power

Multi-VT Cells

Sini Mukundan    March 13, 2019 March 13, 2019    1 Comment on Multi-VT Cells

At lower technology nodes, leakage power is proving to be a major component of power with the lowered supply and threshold voltage. One method to better balance power and timing… Read more »

Back End, Physical Design    leakage, power, threshold voltage
Parasitic NPN & PNP in an inverter

Power Dissipation: Leakage Power

Sini Mukundan    March 4, 2019 March 4, 2019    4 Comments on Power Dissipation: Leakage Power

Part 1: Sources of Leakage Reduction of power consumption is a requirement for semiconductor devices. First let us list the sources of power to understand how to go about reducing… Read more »

Back End, Physical Design    DIBL, gate leakage, hot carrier injection, leakage, power

Body Effect

Sini Mukundan    February 11, 2019 February 8, 2019    No Comments on Body Effect

1. Threshold Voltage Body effect refers to the change in the threshold voltage of the device when there is a difference between substrate(body) and source voltages. Body bias is usually… Read more »

Back End, Physical Design    threshold voltage
CMOS cross section with well ties

Threshold Voltage

Sini Mukundan    February 8, 2019 February 11, 2019    No Comments on Threshold Voltage

To discuss the svt, hvt and lvt cells used for power aware designing, we need to first iterate our understanding of threshold voltage. Let’s consider the NMOS in the above… Read more »

Back End, Physical Design    hvt, lvt, svt, threshold voltage

TCL Training Series – Passing an array as procedure argument

Sini Mukundan    February 7, 2019 February 7, 2019    1 Comment on TCL Training Series – Passing an array as procedure argument

A TCL array is an associative array. i.e. there is an (un-ordered) key-value pair in a TCL array. A simple list of elements as in a perl array or a… Read more »

General, TCL Programming    TCL

Clock Groups : set_clock_groups

Sini Mukundan    February 6, 2019 February 7, 2019    No Comments on Clock Groups : set_clock_groups

Back when I gave an introduction to SDC, I brushed upon `set_false_path` statements between clocks. However, now there is a more efficient way of specifying the the clock exceptions in… Read more »

Back End, Physical Design, STA    asynchronous, false paths, logically_exclusive, physically_exclusive, sdc, set_clock_groups

Two Stage Synchonizers

Sini Mukundan    February 5, 2019 February 5, 2019    No Comments on Two Stage Synchonizers

When an asynchronous signal, or a signal from a block clocked by a different clock is received by a synchronous circuit, it is imperative that it is reliably sampled by… Read more »

Back End, Physical Design, STA    mtbf

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