Body Effect
1. Threshold Voltage Body effect refers to the change in the threshold voltage of the device when there is a difference between substrate(body) and source voltages. Body bias is usually… Read more »
Threshold Voltage
To discuss the svt, hvt and lvt cells used for power aware designing, we need to first iterate our understanding of threshold voltage. Let’s consider the NMOS in the above… Read more »
TCL Training Series – Passing an array as procedure argument
A TCL array is an associative array. i.e. there is an (un-ordered) key-value pair in a TCL array. A simple list of elements as in a perl array or a… Read more »
Clock Groups : set_clock_groups
Back when I gave an introduction to SDC, I brushed upon set_false_path statements between clocks. However, now there is a more efficient way of specifying the the clock exceptions in… Read more »
Two Stage Synchonizers
When an asynchronous signal, or a signal from a block clocked by a different clock is received by a synchronous circuit, it is imperative that it is reliably sampled by… Read more »
Metastability
In digital circuit, the signal is required to be within certain voltage or current limits (logic 0/1 levels) for correct circuit operation. If the signal is within an intermediate range… Read more »
TCL Training Series – upvar
We have seen the command “uplevel” and how to use it earlier. Now, let’s look into a related command upvar. Syntax The TCL language reference manual gives the following description… Read more »
TCL Training Series – uplevel
uplevel is a built-in tcl command that evaluates a script in a different level. Syntax uplevel ?level? arg ?arg …? level here can be number or a # followed by… Read more »
Common Path & Clock Reconvergence Pessimism Removal
Many a time your chip is overdesigned due to undue pessimism in timing calculations. Pessimism in timing analysis makes it difficult for designs to close timing and it is imperative… Read more »
Useful Skew
For clock trees, the traditional way is to go with zero skew or balanced skew. For each of the sinks, the insertion delay is kept to be equal so that… Read more »