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Metastability

Sini Mukundan    January 29, 2019 January 29, 2019    No Comments on Metastability

In digital circuit, the signal is required to be within certain voltage or current limits (logic 0/1 levels) for correct circuit operation. If the signal is within an intermediate range… Read more »

Back End, STA    mtbf, reliability

TCL Training Series – upvar

Sini Mukundan    January 10, 2019 January 10, 2019    3 Comments on TCL Training Series – upvar

We have seen the command “uplevel” and how to use it earlier. Now, let’s look into a related command upvar. Syntax The TCL language reference manual gives the following description… Read more »

General, TCL Programming    TCL

TCL Training Series – uplevel

Sini Mukundan    December 18, 2018 December 18, 2018    No Comments on TCL Training Series – uplevel

uplevel is a built-in tcl command that evaluates a script in a different level. Syntax uplevel ?level? arg ?arg …? level here can be number or a # followed by… Read more »

Scripts, TCL Programming    TCL
Common Path Pessimism Removal

Common Path & Clock Reconvergence Pessimism Removal

Sini Mukundan    May 10, 2018 May 10, 2018    4 Comments on Common Path & Clock Reconvergence Pessimism Removal

Many a time your chip is overdesigned due to undue pessimism in timing calculations. Pessimism in timing analysis makes it difficult for designs to close timing and it is imperative… Read more »

Back End, Physical Design, STA    clock reconvergence pessimism, common path pessimism removal, cppr, sta, timing
Skewed clock to fix timing violation

Useful Skew

Sini Mukundan    May 8, 2018 May 8, 2018    2 Comments on Useful Skew

For clock trees, the traditional way is to go with zero skew or balanced skew. For each of the sinks, the insertion delay is kept to be equal so that… Read more »

Back End, Physical Design    cts, optimization, skew, useful skew

Physical Only Cells: Filler Cells

Sini Mukundan    March 23, 2018 April 4, 2018    2 Comments on Physical Only Cells: Filler Cells

Let us continue with the physical only cells present in the standard cell libraries that ease the digital PD flow. Filler Cells Well Tap Cells Decap Cells Filler Cells Once… Read more »

Back End, Physical Design    DRC, filler, GA filler, physical design flow

Physical Only Cells; Well Taps & Decap Cells

Sini Mukundan    March 22, 2018 May 8, 2018    4 Comments on Physical Only Cells; Well Taps & Decap Cells

In PD flow, you must have come across the term physical only cells. Let us explore a few of them. Well Tap Cells Decap Cells Filler Cells Well Tap Cells… Read more »

Back End, Physical Design    decap, decoupling capacitor, nwell bias, pnr, substrate bias, tap cell
Parasitic NPN & PNP in an inverter

CMOS Latchup

Sini Mukundan    March 21, 2018 March 21, 2018    2 Comments on CMOS Latchup

Latch-Up is a condition where a low impedance path is created between a supply pin and ground. To understand latch up we need to understand the various parasitic components in… Read more »

Back End, General    cmos
Timing diagram for ICG

Clock Gating Checks

Sini Mukundan    March 19, 2018 March 19, 2018    3 Comments on Clock Gating Checks

As we saw in the earlier article on ICG, a gated clock is when you use a logic gate to control or enable to the propagation of clock to certain… Read more »

Back End, Physical Design, STA    hold, icg, setup

String Split in SV

Sini Balakrishnan    October 27, 2017 October 27, 2017    2 Comments on String Split in SV

In our verification environment, we may need to do some kind of string manipulations. In scripting languages like perl, this is done by using just a method (split). In SV,… Read more »

Front End, Simulation Based, System Verilog, Verilog    System Verilog

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