SVA Sequences II – Repetition Operators
There are three different kinds of repetition operators available in SVA viz., consecutive, non-consecutive and goto. For all three operators the number of iterations can be either specified by an… Read more »
Physical Design Flow V: Physical Verification
I. NetlistIn & Floorplan II. Placement III. Clock Tree Synthesis IV. Routing After routing, your layout is complete. Now a number of checks are performed to verify that the drawn… Read more »
SVA Sequences I : Basics
Sequences Sequence is a finite list of System Verilog Boolean expressions which matches along a finite interval of consecutive clock ticks. It evaluates Boolean expressions to true in each clock… Read more »
Code Coverage Fundamentals
Coverage is a metric to assess the progress of functional verification activity. This plays a major role to get a clear picture on how well the design has been verified… Read more »
Physical Design Flow IV:Routing
I. NetlistIn & Floorplan II. Placement III. Clock Tree Synthesis After CTS, the routing process determines the precise paths for interconnections. This includes the standard cell and macro pins, the… Read more »
Physical Design Flow III:Clock Tree Synthesis
I. NetlistIn & Floorplan II. Placement For synchronized designs, data transfer between functional elements are synchronized by clock signals. In a top level digital design, you will have one more… Read more »
Physical Design Flow II:Placement
I. NetlistIn & Floorplan After you have done floorplanning, i.e. created the core area, placed the macros, and decided the power network structure of your design, it is time to… Read more »
Physical Design Flow I : NetlistIn & Floorplanning
This is going to be a series of step-by-step explanation of physical design flow for the novice. I am going to list out the stages from Netlist-GDS in this session…. Read more »
set_timing_derate
set_timing_derate set_timing_derate is a command that lets you constraint the timing. Forget the process variation and OCV for now and let’s uncomplicate and first see how the command works. Timing… Read more »
SVA : System Tasks & Functions
Assertion severity – system tasks In System Verilog, severity of assertion messages is classified by using four system tasks. These are $fatal, $error, $warning and $info. If an action block… Read more »