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SVA Sequences II – Repetition Operators

Sini Balakrishnan    October 13, 2013 October 16, 2013    5 Comments on SVA Sequences II – Repetition Operators

There are three different kinds of repetition operators available in SVA viz., consecutive, non-consecutive and goto. For all three operators the number of iterations can be either specified by an… Read more »

Assertion Based Verification    sequence, sva, System Verilog Assertions

Physical Design Flow V: Physical Verification

Sini Mukundan    October 12, 2013 December 24, 2013    47 Comments on Physical Design Flow V: Physical Verification

I. NetlistIn & Floorplan II. Placement III. Clock Tree Synthesis IV. Routing After routing, your layout is complete. Now a number of checks are performed to verify that the drawn… Read more »

Back End, Physical Design    physical design flow

SVA Sequences I : Basics

Sini Balakrishnan    October 10, 2013 October 13, 2013    4 Comments on SVA Sequences I : Basics

Sequences Sequence is a finite list of System Verilog Boolean expressions which matches along a finite interval of consecutive clock ticks. It evaluates Boolean expressions to true in each clock… Read more »

Assertion Based Verification    sequence, sva, System Verilog Assertions

Code Coverage Fundamentals

Sini Balakrishnan    October 7, 2013 October 13, 2013    17 Comments on Code Coverage Fundamentals

Coverage is a metric to assess the progress of functional verification activity. This plays a major role to get a clear picture on how well the design has been verified… Read more »

Verification    coverage, functional verification

Physical Design Flow IV:Routing

Sini Mukundan    September 1, 2013 December 24, 2013    32 Comments on Physical Design Flow IV:Routing

I. NetlistIn & Floorplan II. Placement III. Clock Tree Synthesis After CTS, the routing process determines the precise paths for interconnections. This includes the standard cell and macro pins, the… Read more »

Back End, Physical Design    physical design flow

Physical Design Flow III:Clock Tree Synthesis

Sini Mukundan    August 7, 2013 April 15, 2014    57 Comments on Physical Design Flow III:Clock Tree Synthesis

I. NetlistIn & Floorplan II. Placement For synchronized designs, data transfer between functional elements are synchronized by clock signals. In a top level digital design, you will have one more… Read more »

Back End, Physical Design    physical design flow

Physical Design Flow II:Placement

Sini Mukundan    July 26, 2013 December 24, 2013    44 Comments on Physical Design Flow II:Placement

I. NetlistIn & Floorplan After you have done floorplanning, i.e. created the core area, placed the macros, and decided the power network structure of your design, it is time to… Read more »

Physical Design    physical design flow

Physical Design Flow I : NetlistIn & Floorplanning

Sini Mukundan    July 24, 2013 July 6, 2019    83 Comments on Physical Design Flow I : NetlistIn & Floorplanning

This is going to be a series of step-by-step explanation of physical design flow for the novice. I am going to list out the stages from Netlist-GDS in this session…. Read more »

Physical Design    physical design flow

set_timing_derate

Sini Mukundan    July 9, 2013 December 20, 2018    10 Comments on set_timing_derate

set_timing_derate set_timing_derate is a command that lets you constraint the timing. Forget the process variation and OCV for now and let’s uncomplicate and first see how the command works. Timing… Read more »

Physical Design    sta, timing

SVA : System Tasks & Functions

Sini Balakrishnan    July 6, 2013 October 13, 2013    3 Comments on SVA : System Tasks & Functions

Assertion severity – system tasks In System Verilog, severity of assertion messages is classified by using four system tasks. These are $fatal, $error, $warning and $info. If an action block… Read more »

Assertion Based Verification    assertions, sva

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