SV Constraint random value generation : Introduction

System Verilog supports three different approaches in verification as follows.
1. Directed Testing
2. Random Testing
3. Directed Random/Constrained Random Testing

Directed testing is the traditional verification approach. In this case, a particular scenario is created for a known feature and set the expectation for the same. So, the features have been verified can be easily identified from the tests itself. This increases the visibility of the design. But there are chances of missing actual bugs in the design, as user can’t develop and run all possible scenarios. Due to the increase in design size and complexity, directed test is not an efficient way for verification of modern designs. Developing and maintaining a large set of directed test suite are incredibly tedious.

In Random Testing, scenarios are created randomly. In this we might be able to find more errors, if we could run the simulations for a longer period of time. So with the limited period of time there is a chance of missing certain bugs.

In directed random/constrained random testing, random values are generated in a controlled manner. In this way most of the important scenarios including corner cases can be verified in the limited time period. This approach requires a complex environment which increases environment development cycle. But efficiency increases a lot.

System Verilog allows users to generate constrained random tests in a very efficient method by using different constructs and methods. User can specify constraints in a compact declarative way. The constraints are then processed by a solver and generate random values that meet the constraints.

SystemVerilog uses an object-oriented method for assigning random values to the member variables of an object.

The myclass class has two random variables addr and data representing 16 bit address and 32bit data values on a bus. There is a constraint which says address must be non-zero.
The randomize() method is called to generate new random values for the above class object.

In the above code, c1.randomize() randomizes all the random values in the class object which is shown in the simulation output. Also note that there is no zero value for address due to the constraint given.

randomize() with
Constraints can be applied inline as well. In the below code there is one more constraint on the address. The class mysubclass is inherited from myclass, so it inherits all of the random variables and constraints of the parent class and adds a random variable called ar that is used to control the address range using another constraint.

When a mysubclass object is randomized, values for addr, data, and ar are computed so that all of the constraints are satisfied. Objects can be further constrained using the randomize() with construct, which declares additional constraints in-line with the call to randomize().
In the above code, randomize() with ar == low -> means generate random values by satisfying the constraint -> address should fall in the range of 0 to 127.

Constraint_mode() & rand_mode()
constraint_mode() method can be used to enable or disable any named constraint block in an object.

In the first part of the above code, the constraints for address are disabled using constraint_mode(0) and enabled using constraint_mode(1). The difference in the address values can be seen in the simulation output.
Similarly, the rand_mode() method can be used to enable or disable any random variable. When a random variable is disabled, it behaves in exactly the same way as other nonrandom variables.

In the above code addr is disabled using rand_mode(0). The constraints also have to be disabled otherwise tool will issue error on constraint mismatch. In this case addr is behaving as a non-random variable.

pre_randomize() and post_randomize()
To perform operations immediately before or after randomization, two built-in methods pre_randomize() and post_randomize() are available in SV. These methods can be overridden with the desired functionality.

The random stimulus generation capabilities and the object-oriented constraint-based verification methodology enable users to quickly develop tests that cover complex functionality and better assure design correctness.

More information above SV constraint value generation can be seen in the SV-Constraint random value generation series.

2 comments on “SV Constraint random value generation : Introduction

  1. Manish Sharma

    1)how to write the constraint for an ascending order dynamic array.
    2) highly appreciate if more examples for solve-before ans functional verification would be here as interviews now a days are asking a lot from CRT and FC

  2. babu

    Hi sini balakrishnan, Your posts are really good and making me more interest, I am having very much interest on vlsi verification and also working now, but i am not good in verification as I am not having basics of verification. So can you please give any suggestion like from where should I start to learn basic of verification ? I kindly request Please share any simple protocol TB in SV and UVM so that will help me out…thanks a lot in advance,,,


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