SVA Basics: Bind

Binding SVA module to design can be done using system verilog bind statement. This is semantically equivalent to instantiation of SVA module. The bind directive can be specified in a module, interface or a compilation unit scope.

There are many ways binding can be done. Following section discusses these.

Normal Bind Binding fifo to fifo_sva assertion module can be done as follows

bind fifo fifo_sva fifo_sva_inst (.clk(clk_i ),.rst_n(rst_n_i),.data_i(data_i),.data_o(data_o),.wr(wr_i),.rd(rd_i))

Bind using Implicit port connections By using this method, port names need not be specified and all ports will be accessible to assertion module.

bind fifo fifo_sva fifo_sva_inst(.*);

Bind to a lower level module Hierarchy needs to be specified along with the bind statement.

bind $root.vhdl_top.sub1_inst.sub2_inst slave_sva_check slave_bind(..) //Design with vhdl top (in IFV tool) bind vlog_top.sub1_inst.sub2_ins slave_sva_check slave_bind(..) //vlog

Bind using different parameters/generic Passing parameter values in bind can be done in the following way.

bind fifo fifo_sva #(.wordsize (8),.fifosize (32) ) fifo_sva_inst (.clk(clk_i ),.rst_n(rst_n_i), .data_i(data_i),.data_o(data_o), .wr(wr_i),.rd(rd_i))

This helps to develop generic assertions.

Bind to a instance of a module If there are multiple instances of fifo module, and need to bind assertion to two of the instances (fifo1,fifo2). This can be done in the following way.

bind fifo: fifo1, fifo2 fifo_sva fifo_sva_inst2 (.clk(clk_i ),.rst_n(rst_n_i),.data_i(data_i),.data_o(data_o),.wr(wr_i),.rd(rd_i)) bind fifo: fifo1 fifo_sva fifo_sva_inst1 (.clk(clk_i ),.rst_n(rst_n_i),.data_i(data_i),.data_o(data_o),.wr(wr_i),.rd(rd_i)) //binding to only fifo1 inst

So we can make the design untouched by developing assertions in a separate module and by using any of the above bind statements.