SVA Basics: Bind

Binding SVA module to design can be done using system verilog bind statement. This is semantically equivalent to instantiation of SVA module. The bind directive can be specified in a module, interface or a compilation unit scope.

There are many ways binding can be done. Following section discusses these.

Normal Bind
Binding fifo to fifo_sva assertion module can be done as follows

Bind using Implicit port connections
By using this method, port names need not be specified and all ports will be accessible to assertion module.

Bind to a lower level module
Hierarchy needs to be specified along with the bind statement.

Bind using different parameters/generic
Passing parameter values in bind can be done in the following way.

This helps to develop generic assertions.

Bind to a instance of a module
If there are multiple instances of fifo module, and need to bind assertion to two of the instances (fifo1,fifo2). This can be done in the following way.

So we can make the design untouched by developing assertions in a separate module and by using any of the above bind statements.

3 comments on “SVA Basics: Bind

    1. Sini Balakrishnan Post author

      Swastika, You can use $nc_mirror if you use Incisive tool.

      For eg:
      top_tb.dut:inst_block1:inst_block2:sig1 signal can be mirrored to sig1 in the following way.

      Please check in the user manual if you use other simulators.

  1. Debashis

    Hi Sini, I have a basic doubt. Please help.

    bind module1 dbg_client_mux_if if_dbg_client_port_0_mux_0(
    .idebug0 (tb.u_blk1.mux0_identify[31:0]),


    In the above code snippet,if my understanding is correct, it will bind the signals of dbg_client_mux_if with interface of module1.

    But in top level module “module1”, there is no interface/signals of name “mux0_identify” and no instantiation of “tb” inside “module1”.

    So my doubt is , how does the bind happens. How it is able to see “tb” ?

    the interface do exists in tb.u_blk1.mux0_identify.


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