SVA : System Tasks & Functions
Assertion severity – system tasks
In System Verilog, severity of assertion messages is classified by using four system tasks. These are $fatal, $error, $warning and $info. If an action block is specified, user-defined severity can be created by using these system tasks.
Every assertion failure has an associated severity which can be specified in the fail-statement block. If assertion does not have a fail-statement block, then by default $error system task will be called with default message.
The syntax of severity system tasks except $fatal is identical to $display, but for $fatal, error code will be the first argument.
**- $fatal:**This generates a run time fatal error that terminates the simulation with the specified error code. The error code is mandatory and which will be returned to the operating system. The $fatal ends the simulation, that means it has an implicit call of $finish.
$fatal [ ( error_code [ , message_string { , message_argument } ] ) ]
**- $warning:**This generates run time warning which can be suppressed by using tool options.
$warning [ ( [ message_string { , message_argument } ] ) ]
**- $error:**This generates a run time error that does not terminate the simulation.
$error [ ( [ message_string { , message_argument } ] ) ]
$error("%m: data_in not stable for %0d clocks",n);
**- $info:**This generates information to the user and indicates that the assertion failure carries no specific severity.
$info [ ( [ message_string { , message_argument } ] ) ]
Assertion control – system tasks
For controlling assertions and coverage, system Verilog provides three system tasks, which are $asserton, $assertoff and $assertkill.
- $assertoffThis stops the evaluation of all specified assertions until a subsequent $asserton. The assertion that is currently evaluated, including execution of the pass or fails statement is not affected.
**- $asserton:**This re-enables the execution of all specified assertions. If it is called without any argument, it turns on the assertions for the entire design which is same as $asserton(0, top).
With argument: $asserton(3) - Turns on all assertions on top level and the next three sub-levels below. $asserton(0, top.sub1.sub2) Turns on the assertions for the entire hierarchy starting at the scope top.sub1.sub2
**- $assertkill:**This aborts immediately the execution of any currently evaluated specified assertion and then stops the evaluation of all specified assertions until a subsequent $asserton.
Assertion action control system tasks
$assertpasson, $assertpassoff, $assertfailon, $assertfailoff, $assertnonvacuouson, $assertvacuousoff are action control system tasks in SVA.
Vector analysis - system functions
**- $onehot (expression):**This returns TRUE, if one and only one bit of the expression is high. Return type: bit
**- $onehot0 (expression):**This returns TRUE, if at most one bit (i.e., zero or one bit) of the expression is high It is same as $onehot(expr) || expr == ‘b0. Return type: bit
**- $isunknown (expression):**This returns TRUE, if any bit of the expression is either X or Z. It is same as ^ === ’bx. Return type: bit
DataTr should never be unknown property prop_check_unknown(clk,reset_n,DataTr); @(posedge clk)
disable iff (!reset_n) not $isunknown(DataTr); endproperty : prop_check_unknown
**- $countones (expression)**This returns the number of 1s in a bit vector expression. X and Z are not counted towards the number of 1s. Return type: integer
Value change system functions
The system functions $rose, $fell, $stable and $changed are used to detect changes in values between two adjacent clock cycles. It uses sampled values of the expression with return type of bit.
- $rose:
This returns TRUE, if the LSB of the expression changed to 1. Otherwise, it returns false. Main difference with posedge is that, posedge returns event, but $rose returns boolean value. Posedge cannot be used with expression as it returns event.
$rose (expression [,clocking_event] )
Data must be stable at rising clock edge of shift clock $rose(dif_sh_clk_o) |-> $stable(dif_ms_in_i);
**- $fell:**This returns TRUE, if the LSB of the expression changed to 0. Otherwise, it returns false.
$fell (expression [, clocking_event] )
Flush operation operation of FIFO property prop_wr_flush; @(posedge clk) $fell(write) |=> (wr_ptr == 0) && !full_o; endproperty : prop_wr_flush
**- $stable:**This returns TRUE, if the value of the expression did not change.
$stable (expression [, clocking_event] )
If there is a change in data_in, it must be stable for next "n" clock cycles. property prop_data_stability; @(posedge clk_i)
disable iff (!reset_n_i) !$stable(data_in) |=> $stable(data_in) [*n]; endproperty : prop_data_stability
**- $changed:**This returns TRUE, if the value of the expression changed.
$changed (expression [, clocking_event] )
$changed(out) |=> (out = inp);
Value access system functions**- $sampled:**
$sampled (expression [, clocking_event] )
This returns the current sampled value of the specified expression. As the assertions use sampled values, the use of $sampled in assertions besides the disable-statement and the action block is redundant. When $sampled is invoked prior to the occurrence of the first clocking event, the value of X is returned.
**- $past:**This returns the sampled value of the specified expression that was present number of clock cycles in other words number of ticks prior to the time of evaluation of $past. The number of cycles must be one or greater and by default it takes the value as 1. If the specified clock tick in the past is before the start of simulation, $past returns a value of X.
$past (expression1 [, number_of_clk_cycles] [, expression2] [, clocking_event] )
assert(data_out |-> ($past(data,2) || $past(data,3)));