System Verilog : Rand & Randc

There are two type-modifier keywords available in system Verilog to declare class variable as random.

Variables declared with the rand keyword are standard random variables. Their values are uniformly distributed over their range.

Variables declared with the randc keyword are random-cyclic variables that cycle through all the values in a random permutation of their declared range.

In the above code all names are declared as rand (students_r) and randc (students_rc).

Randomization result for students_r and students_rc are shown above. In this we can see that students_rc (randc) cycle through all the values in a permutation.

Another example to show that randc cycle through all the values in a permutation.

1 comment on “System Verilog : Rand & Randc

  1. kishore

    Superb Explanation.
    I tried to learn System verilog long before.
    I had lot of doubts.
    Even after searching several web, my doubts never cleared.
    If i have seen your post several years before, i would have benefited a lot.
    There would have been a change in my career.

    All Post super………………….


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