Verilog: Timescales

As we are aware, compiler directive `timescale in Verilog is a tricky topic and have many discussion around it.

Timescale specifies the time unit and time precision of a module that follow it. The simulation time and delay values are measured using time unit. The precision factor is needed to measure the degree of accuracy of the time unit, in other words how delay values are rounded before being used in simulation.

Let’s have a look into it and see how time units and precision are taken to calculate simulation time.

In the examples, following time scale /time precision combinations are used.

The rval changes in different time-steps but due to the differences in timescale directives the simulation time varies.

In the below code, timescale is `timescale 1ps / 1ps.

To find out number of digits taken after decimal, first divide time scale with time precision. The exponent number will be your result.

Here, 1ps/1ps = 1 = 100, as the result is 100, NO digit will be taken after decimal. So 10.566601 will be 11 and next time step 21.546604 will be just 22.

Check below result to see all simulation time for rval. Also note that simulation ends at 100 PS.

Now, let us check one more example. In module timescale_check2, timescale is 1ns / 1ps.

Timescale/Time Precision = 1ns/1ps = 1000 = 103 So 3 digits after decimal will be used. In this case 10.566601 becomes 10567 and 21.546604 becomes 21547.

Below examples show simulation results for timescales 100ns/1ns, 1ms / 1us and 10 ms / 10 ns.

15 comments on “Verilog: Timescales

  1. satish

    Thanks a lot for the detailed explanation with examples.
    Can you please try to explore more on $timeformat and it’s impact on multiple files?

  2. muvva


    your explanation is very nice, but still i had a small difficulty.

    according you both 1ps/1ps and 1ns/1ns has to give same answer as both give 10^0 only, but i am getting different results.

    with no provision i failed attach the image, if you give your mail id i can post the simulation results.

    thanking you,

  3. Sarah

    I think these examples are extremely confusing. Mainly because of this line:

    $monitor("TimeScale 1ms/1us : Time=%0t, rval = %d\n",$realtime,rval);

    It could be improved by changing it to this:

    $monitor("TimeScale 1ms/1us : Time=%0f, rval = %d\n",$realtime,rval);

    Looking at output from the authors code all the times appear to be multiplied by the time-unit/time-precision, and that’s not what’s really happening. $realtime is a real/float and should be printed as such.

  4. Srinivasan

    Great work.
    I have few doubts.
    How can I represent a rational number/floating point number in verilog. Example 12.5 or 12.246
    ‘Timescale is used only for simulation purposes.
    According to my knowledge, real keyword can be used , but again it’s a not synthesize or fixed point representation (synthesizable) and floating point rep are used .
    Accuracy in the above mentioned cases are less. What should be done to fetch good accuracy.
    Can you please help me with your suggestions.

  5. Srinivasan

    Great work. As ‘timescale is used in test bench . If I have to represent a rational number in verilog.example 12.5 or 11.246. how should it be done.
    From my knowledge, keyword real is available, but again it’s not synthesizable. Other ways are fixed point (synthesizable )or floating point representations. But accuracy becomes less.
    Can you please help me with suggestions.


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