Verilog: Timing Controls

Timing Controls

Timing control statements are required in simulation to advance time. The time at which procedural statements will get executed shall be specified using timing controls. Delay based, event based and level sensitive timing controls are available in Verilog. Each of these are discussed below.

Delay Based Timing Control

In this, timing control is achieved by specifying waiting time to execution, when the statement is encountered. The sybmol “#” is used to specify the delay. There are 3 ways, delay based timing control can be specified.

  • Regular Delay Control

    In this delay will be specified on the left of the procedural assignment as a non-zero number. In the below code, execution of line 11 to 14 statements are controlled by some delays. The statement b = 1 will be executed at time 10 and others at time 30,35 and 45. Refer simulation result for more details.

  • Intra-assignment Delay Control

    In this case, delays will be specified on the right hand side of the assignment operation. The RHS expression will be evaluated at the current time and the assignment will be occurred only after the delay. The statement a = #5 (b + c) and rval = #20 L_DELAY + a – 4 are intra-assignment delay control statements.
    Value of b and c are evaluated at time 45, but assignment to ‘a’ will happen only at time 50. The same way L_DELAY + a – 4 will be calculated at time 50 and assignment to rval will happen at time 70.

  • Zero Delay Control

    Zero delay control statement specifies zero delay value to LHS of procedural assignment. This is a method to ensure that the statement is executed at the end of that simulation time. That means, zero delay control statement is executed only after all other statements in that simulation time are executed. Here, a,b,c are executed different values in two initial block, one using normal assignment and other using zero delay. This example shows that how assignments will happen in the simulation.

Event Based Timing Control

In this, execution of a statement or a block of a statement is controlled by an event. Regular, named and event OR control are different types of event based controls.

  • Regular event control

    Execution of statement will happen on changes in signal or at a positive or negative transitions of signals. For example posedge of clock, negedge of reset etc.

  • Named Event Control

    Event will be declared using keyword ‘event’ and is triggered by using the symbol ‘ -> ‘. In the below example the event ‘received’ is declared and is triggered when pkt_done is high. Once event is triggered, always block at line 23 will get executed.

  • Event OR control

    The transitions of signal or event can trigger the execution of statements as shown below.

Level Sensitive Timing Control

This waits for a certain condition to be true. In the below example, it waits for xor-ctrl bits to be 1, and then do the assignment to out.

5 comments on “Verilog: Timing Controls

  1. Gowri Shankar


    Regards for the day.

    Please let me know the difference between

    always @ (posedge clock)
    @(posedge clock)

    Because according to what i understand is both get triggered on positive edge then why use two different methods for same operation

    Thank you

    1. Sini Balakrishnan Post author

      Hi Gowri Shankar,

      How did you use @(posedge clock) in your design ?

      In verilog this has to be used in either always or initial block.

      Difference between always @(posedge clock) and @(posedge clock) (in the initial block) is, in the first case, it executes whenever there is a change in the clock from 0 to 1. But in the second case it executes only for the first posedge change.

      In the below example
      check_posedge_clk_2 module uses @posedge of clk and
      check_posedge_clock uses always @posedge clock.

      check_posedge_clk_2 executes only once, but other one executes for all the posedge changes of the clock till $finish.

      Hope this helps.

  2. Rakesh

    dear prudhvi,
    | is a doing bit wise operation ; for example a is 4 bit and b is 4 bit it will gives another 4 bit output.

    or: here based on any one of the inputs of a,b changes it will occurs the below procedural code


    can event control statement as :-

    always @(posedge clk)
    @(a or b)
    k1 = a;
    k = 0;
    k2 = b;
    k3 = 0;
    is synthesizable?
    It is showing me some error as
    Multiple event control statements in one always/initial process block are not supported in this case.


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