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Clock Gating Checks

As we saw in the earlier article on ICG, a gated clock is when you use a logic gate to control or enable to the propagation of clock to certain parts of logic. Take for example, the AND based clock gate below.Clock gating checks are timing checks done by your STA tool to ensure that you get a glitch free gated clock signal. With different types of gates, you are ensuring that the EN doesn’t change at the non-controlling state of the clock.

AND based clock gate

Note: All the below checks are for AND gate based clock gating.
For the circuit above, when the enable signal EN is high, the Clk signal is transmitted to Gclk. When EN is low, irrespective of the Clk value, GClk output is 0. You can also say that when Clk is low, changes in EN signal does not cause any change in Gclk output. Only when Clk is high, does EN changing cause an immediate change in output, I.e. Gclk. Hence in this case, 0 is the controlling state of the Clk. For a non-glitchy or unclipped GClk signal, you should ensure that EN changes only when Clk is low. If EN changes when Clk is high, it will cause either a setup or hold violation as given below.
1. Setup check: The clock gating setup check is used to ensure the EN is are stable before the clock is active. A clock gating setup failure can cause a glitch at the leading edge of the clock.
2. clock gating hold check is used to ensure that the EN is stable while the clock is active. A clock gating hold violation causes a glitch at the trailing edge of the clock pulse.

Timing diagram for ICG

In case1 above, EN is changing when the Clk signal is low. There is no possibility of a glitch in this case. In case 2, EN changes before the clock reaches the level where it is permissible for the enable to change. This causes a glitch at the trailing edge of the clock. In case 3, the EN goes high after the clock’s active edge, causing a clipping at the rising edge.

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