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Physical Only Cells: Filler Cells

Let us continue with the physical only cells present in the standard cell libraries that ease the digital PD flow.
Filler Cells
Well Tap Cells
Decap Cells

Filler Cells
Once you have completed placement and routing, there are usually gaps left in the layout where you do not have any standard cells present. It is not possible to abut every cell available as that would cause routing issues due to high congestion and also give you a poor layout in terms of timing. So, if you say you have 70% utilization, you can expect around 30% of the area unfilled. If you do DRC check now(in a tool that can give you base layer DRCs), you can expect to see spacing violations like “NWell minimum spacing not met”. This is where the filler cells come in. For a clean layout you need NWELL continuity. It is imperative that you do not have well or moat spacing less than the minimum spacing(Even though you can space them apart with spacing greater than the minimum spacing, it is going to be tricky in a row of standard cells. Also, in a tap-less library, you need the fillers to continue the well-tieoffs as even if you space them with distances larger than minimum well spacing, you will have continuity error in power connection unless each such hroups have their own tie cell.) Filler cells are cells with no logical functionality, but it continues the base layers like NWELL and have the VDD/VSS pins matching the rest of the standard cells. You will have one such filler with the smallest tile width in the standard cell library among other sizes, which can fill any gap if your placement followed the placement grid.

In cadence’s Innovus tool, the following commands can be used to automatically place the fillers.

You can delete the fillers in only specific area, or only specific cells. Fillers can be added before routing, so any metal DRCs can be taken care of by the router. However you need to delete them before doing any post routing optimization as filler addition will cause 100% utilization of the core. This will cause the placement of any new cell addition due to optimization commands to fail.

Gate Array Filler Cells
Gate array filler cells area available in some libraries which come in handy while doing ECOs. These are some special cells, which can be programmed into one (or more) type of standard cells by just changing the metal connections. These are placed in the filler cell placement stage as any regular nwell filler. While doing metal only ECOs, the tool will pick the corresponding cell from the library to replace the original filler.

e.g. If an AND gate needs to be added, the tool will see which of these gate array fillers can be replaced with special AND cells with matching base layers and swap the filler with the AND cell. An example command in Innovus tool to use these is
ecoPlace -useGAFillerCells

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  1. Pingback: Physical Only Cells; Well Taps & Decap Cells – VLSI Pro

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