Engineering Change Order or ECO is how you incorporate last minute changes in your design. ECO saves money and time and is prevalent in the industry. When I talk ECO, I am talking about ECOs in the layout. So typically you start with an ECO on the gate level netlist. The designer need to edit the gate-level netlist, make the same changes in RTL, and then pass all verifications before it is passed on to layout. Make sure the ECO pass formal and functional verification before you start editing your layout. There are two types of ECOs and similar design flows are used by the PnR tool for both except the variable or command related to “freeze_silicon”.

Unconstrained ECO/All Layer ECO
An all layer ECO is typically done before mask generation. There is no restriction on the changes permitted in the layout. You need to have a robust ECO flow ready as you are gearing up for tapeout. ECOs can be done at any stage in the design flow, post-place, post CTS and post-route. ECOs are used to

  • Fix timing violations – There may be constraints that were missed on specific nets. An ECO can add buffers/delays to control the timing behaviour of the design.
  • Fixing bugs – Last minute bugs are the norm. As the tapeout frenzy catches, the simulations might just throw up that bug everyone missed till then. If it can be fixed by an ECO, engineers prefer it in cases where the runtimes and complexity of the design is large enough to warrant a preservation of the existing results/database.
  • Adding functionality – You may not see a lot of post-signoff ECOs in this category. But smaller feature additions can be done using ECOs rather than redoing the design and it can happen.

An unconstrained ECO typically has the following stages.

  1. Adding/Deleting Cells – At this stage, there is no restriction on adding the cells other than design/layout constraints.
  2. Updating the connections – The net connections needs to be updated for the existing and newly added cells.
  3. Placement – Tools can automatically place ECO instances, however I find it better to manually place them for best performance.
  4. Routing – Today’s tools can automatically identify the changed nets and route them.

Even though you typically use unconstrained ECO flow before tapeout and as part of your PnR flow, it can also be done after tapeout. There is no savings in mask generation costs, but the design cycle can be significantly reduced if the required changes are minimal.

Freeze Silicon ECO/Metal Mask ECO
These are done after tape-out and saves significant costs in mask generation by targeting only a few layers for new mask generation. The base layers are all frozen and cannot be changed. All or some of the metal layers are changed to achieve the required functionality of the ECO. The reasons for the ECO and the flow stages stay essentially same; but with some significant differences.

  • Adding/Deleting Cells – No cells can be added or deleted. Technically you can replace cells if the base layers stay the same (say different TIE cells). However, this may be difficult to control.
  • Updating the connections – The net connections needs to be updated.
  • Placement – No ECO placement is done, as there cannot be any addition of cells.
  • Routing – Today’s tools can automatically identify the changed nets and route them.

A freeze silicon ECO typically used spare cells available in the design. These are cells sprinkled in the design in anticipation of use in an ECO. See my article on Spare Cells to know about inserting and placing spare cells.

Example scripts for IC Compiler
ECOs can be done either using database commands or using a modified netlist, typically referred to as an ECO netlist. Because you are editing the database, make sure you save your existing cell before starting the ECO.

1. An all metal layer ECO using database commands.

## ECO commands
size_cell {u_i2c_slave/U3_ICC_cts} stdlib/BUFX8
insert_buffer {ck_rst_gen/U29/Y } {stdlib/BUFX2}
create_cell {xlm48901/eco_diode_1} {ANTENNA5}
set_attribute [get_cells -all {xlm48901/eco_diode_1}] origin "2519.127 0.000"
connect_net {xlm48901/adc_l_enable} {xlm48901/eco_diode_1/A}

##IC place & route of the ECO cells
route_zrt_eco -utilize_dangling_wires true -reroute modified_nets_first_then_others

2. A metal mask ECO using verilog. You can turn on or turn off the freeze_silicon status by the command `set_freeze_silicon_eco`.

set_freeze_silicon_eco -report

eco_netlist -by_verilog_file {./eco.v} -preserve_routing -freeze_silicon
route_zrt_eco -utilize_dangling_wires true -reroute modified_nets_first_then_others

Note that both methods can be used for metal mask only or all layer ECOs.

10 comments on “ECO

  1. charan


    Can you explain me about the EndCap cells, what is their basic functionality, why we are using in lower technologies only.
    I have studied many blogs are all confusing me.

  2. plainspeak


    Wanted to ask you a question about metal ECO done for fixing a silicon issue. Let’s say there are around 40k cells in the chip and there is a requirement of ECO which takes approximately usage of 25 spare cells. Let’s assume that utilization is around 60%. Would the tool be able to do the required changes with only metal change?

    1. Sini Mukundan Post author

      It is possible. Depends on how many spare cells you have placed and if they are close enough to the required modules to meet timing.

    1. Sini Mukundan Post author

      Spare cells are used for ECO.
      Some libraries may have standard cells named as _eco, which are a kind of filler cells which can be converted into certain gates by metal change. These are also used for eco.

  3. Pingback: Physical Only Cells: Filler Cells – VLSI Pro

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