Physical Design Flow II:Placement

I. NetlistIn & Floorplan

After you have done floorplanning, i.e. created the core area, placed the macros, and decided the power network structure of your design, it is time to let the tool to do standard cell placement. The tool determines the location of each of the components (in digital design, standard cell instantiations) on the die. Various factors come into play, like the timing requirement of the system, the interconnect lengths and hence the connections between cells, power dissipation etc. The interconnect lengths depend on the placement solution used, and it is very important in determining the performance of the system as the geometries shrink.Placement also determines the routability of your design.

Placement does not just place the standard cells available in the synthesized netlist. It also optimizes the design, thereby removing any timing violations created due to the relative placement on die.

From a user perspective, these are the things important in placement.

  1. High fanout net synthesis
    High fanout nets other than clocks are synthesized at the placement stage. In logic synthesis, high fanout nets like reset, scan enable etc are not synthesized. You should verify that the SDC used for PnR should not have any `set_ideal_network` or `set_dont_touch` commands on these signals. Also, make sure you set an appropriate fanout limit for your library using the command `set_max_fanout`.

    e.g. `set_max_fanout 20 [current_design]`

    If a driver has too many loads, it will negatively affect the delay numbers and transitions values. After placement, look for any fanout violations in the timing report.

  2. Use Ideal clock
    You are going to synthesize your clock later in the design. So make sure you define the clocks as ideal. If you don’t, HFN synthesis will be done on the clock. Clock constraints like skew or clock buffers are not used, and effectively your clock tree is messed up. In IC Compiler, you can use the following command to make sure clock is not propagated.
    `set_ideal_network [all_fanout -flat -clock_tree]`
  3. Control Congestion
    Congestion needs to be analysed after placement and the routing results depend on how congested your design is. Routing congestion may be localised. Some of the things that you can do to make sure routing is hassle free are:

    • Macro-padding: Macro padding or placement halos around the macros are placement blockages around the edge of the macros. This makes sure that no standard cells are placed near the pin outs of the macros, thereby giving extra breathing space for the macro pin connections to standard cells.
    • Maximum Utilization constraint: Some tools let you specify maximum core utilization numbers for specific regions. If any region has routing congestion, utilization there can be reduced, thus freeing up more area for routing.
      `set_congestion_options -max_util .6 -coordinate {837 114 1103 918}`
    • Placement blockages: The utilization constraint is not a hard rule, and if you want to specifically avoid placement in certain areas, use placement blockages.
  4. Scan chain reordering
    In a less complex design, you don’t usually do scan reordering. However, sometimes it may become difficult to pass scan timing constraints once the placement is done. The scan flip flop placements may create lengthier routes if the consective flops in scan chain are placed far apart due to a functional requirement. In this case, the PnR tool can
    reconnect the scan chains, to make routing easier. A prerequisite for this option is a scan DEF for the tool to recognise the chains.
  5. TIE cells
    In your netlist, some unused inputs are tied to either VDD/VSS (or logic1/logic0). It is not recommended to connect a gate directly to the power network, so you can use TIEHI or TIELO cells if available in your library for the same. These are single pin cells which effectively ties the pin it connects high or low. After placement, dump out a netlist and serach for direct pin connections to the PG rails (other than power pins). There shouldn’t be any if you are using tie cells.

    In IC Compiler, use the following commands to connect tie cells.

    set getTiePins [get_pins -of [get_nets -all -hier {VDD VSS}]]
    connect_tie_cells -objects $getTiePins -obj_type port_inst \
     -tie_high_lib_cell TIEHIX1 -tie_low_lib_cell TIELOX1 -max_fanout 1

    TIE cells insertion flows differ slightly between tools, so go through the help.

  6. Spare cells Read this article on spare cell placement.
  7. Timing
    Your clock is not propagated, hence you have a zero skew at this point. Your timing reports should look pretty good. Make sure fanout constraints are met.

After placement, verify that all cells are placed on rows without any overlaps. You might find the following commands useful depending on your design.
report_level_shifters -verbose`

III. Clock Tree Synthesis
IV. Routing
V.Physical Verification

44 comments on “Physical Design Flow II:Placement

  1. sharan

    I had seen, virtual placement or floor planning(any of two) option in ICC. Where we check whether there is any congestion for routing signals are not?.
    This helps us to to again increase or adjust our core aspect ratio.
    Is this concept correct , please correct me

    1. Sini Mukundan Post author

      I think virtual placement is for rough macro placement. It may be useful. Personally I place macros manually, using flylines for reference. However, do try the tool placement for an initial location.

  2. ameer

    hey hi sini

    i’ve come across a typical problem.

    after doing the floorplanning,PG planning and placement of standard cells in the design. when performing a legality or check place command, i’ve seen violations such as macros are overlapped with the placment blockage. can you please give some info why did this scenario arise and how to resolve that.
    Note: the Legality problem is not due to standard cells but due to macros??

    revert back ASAP

    1. Sini Mukundan Post author

      As long as the overlap is between a macro & placement blockage, and you have added the placement blockage to keep other blocks away from the macro, it is alright to ignore the overlap error.

  3. Sarath Chandra

    Hi Mam,
    What’s the difference between “create_placement” and “place_opt” commands?
    I couldn’t get any info on create_placement anywhere.So please suggest me any websites if possible.

    1. Sini Mukundan Post author

      The best resource for tool commands are the websites for the tool vendor itself.

      create_placement does a coarse placement for helping with floorplanning, and place_opt is the actual placement command you will use.IC Compiler tool command reference should also have the information you seek.

  4. Gokulnath

    Hello Mam,

    will u please explain in detail about scan chain?
    How to create scan chain?
    When the scan chain will be created?

    1. krishna

      In Scan chains, we place a MUX in front of every sink, so that with the enable pin we can test the design with different techniques like MBIST,ATPG etc.
      Scan chain need to function with a low frequency, this frequency is different from that of the actual frequency of the design
      Scan chains would be created well before placement of the design .

  5. Koushik Mahanta


    I want to know:

    a) Is it necessary to fix all the timing violations after the ‘placement’ stage ?

    b) During ‘placement’, the tool might have already tried to meet timing using techniques like: High Fan-out synthesis,cell-sizing,cloning, logic re-structuring etc. If after placement, timing violations are still there, what techniques are to be used to fix timing violations after placement ?

    c) Could you list some useful commands (Synopsys IC Compiler) which are frequently used to fix timing after placement ?

    1. Sini Mukundan Post author

      A. Not necessarily. But it advisable to look at all timing reports after placement to see none are due to wrong constraints like huge input or output delay specifications.
      b. Wait till after cts to fix all if placement didn’t fix some. Hold violations make sense only after cts.

  6. Milind Priyadarshi

    Hello mam,
    I want to know how the nomenclature method for MACROS ie SRAM cells.
    I have a large netlist file and i am unable to identify the MACRO/SRAM hierarchy as i am facing difficulties in identifying them.
    Actually i am designing a EDA tool for placing MACROS manually.

    1. Sini Mukundan Post author

      That’s a good initiative! I don’t know how to identify it from the netlist though. In various companies I have worked, I have seen very differing names used, typically depending on the memory generator software.

      If you are using a P&R tool, you can identify macros by the cell property. Again, I don’t think either EDI or ICC can differentiate between a custom macro cell and memory. Do explore though. I would like to be proved wrong.

      Have you thought about giving the memory cell master list as an option to the tool? It won’t be as automated, but still useful if the placement quality is good.

    1. Sini Mukundan Post author

      That is specific to your design. You need to analyse the reports to see why you are seeing the violation.

    2. krishna


      If the violation what u observe is to a certain limit, then u can reduce it once CTS has been done, because once clock gets propagated, the actual delay between clock sinks would be known and this will reduce the timing violations.

      First of all try to understand why you find timing issue once the design is placed?

  7. naresh

    Hello mam,
    Generally we are adding ENDCAPs for to avoid drc violations, and cell characterization what is meant by cell characterization and well tie-off

    1. Sini Mukundan Post author

      1. End caps are for maintaining the well according to your process requirement. If you look at the endcaps after placements they just create an nwell/hwell ring around your digital. It is just an easier automated way of meeting DRC rather than drawing the ring by hand.

      2. Cell characterization refers to the determination of std cell values for use in digital flow. After measuring the values for various PVT corners, .lib cells are generated for use in digital design flow.

    1. Sini Mukundan Post author

      You can find the pin that is causing the transition violation for the net, and either upsize the driver(previous Y) or add a buffer.

  8. sivakumar

    Hello mam,
    suppose if i am implementing one design both in 65nm and 40nm technology what type of issues we faced in 40nm compared to 65nm?

    1. krishna

      We come across cross-talk violations mainly when we migrate to a lower technology node.
      The design need to be closed in multiple corners due to the effect of temperature inversion.
      corners= (cell delays+ wire delays)* modes = Analysis views
      cell delays= slow, fast,typical
      wire dealys= RCbest, RCworst, Cbest, Cworst, typical
      Here while taking wire delays into consideration we come across temperature inversion concept
      modes= functional mode, test mode etc.

  9. krishna


    what should be done if violations occur after placement?
    If at all it needs to be cleared , what are the techniques ?? can we move forward in the design if we have a large amount of negative slack after placement?

    1. Sini Mukundan Post author

      If there are numerous paths with huge negative slack, it will be difficult to meet once you have propagated clock and further routing.
      The tools have options to reduce the slack after placement, but the ideal way to proceed is by analysing the timing reports and understanding why there is negative slack. If this is due to some bottleneck that needs to be addressed by design.

  10. krishna

    As you said, the cells which cause violation may be optimized in further design stages, how can a bottleneck analysis be advantageous at this stage?
    Kindly provide me an example.

    And one more thing, who will suggest that a margin of slack can be tolerated after placement to move forward in the design?

    1. Sini

      You need to look at the violating paths and see if these are all caused due to same cells. Fixing one or two instances in the path can get you better results, instead of the tool trying to fix by brute force each and every path individually. Of course this may not be your issue. Every design is different.

      It’s your call as the layout designer. Your goal is to get the design timing clean, and if you find that the paths are something you can fix later on, you can move ahead.

  11. krishna

    Can ecoChangeCell command be used after placement of the design?
    May I know the command utilized after placement to fix particular number of paths having violations are all caused due to same cells?

    1. Sini Mukundan Post author

      Can ecoChangeCell command be used after placement of the design? — Yes. You might have to unfix and remove any dont_use if there.

      May I know the command utilized after placement to fix particular number of paths having violations are all caused due to same cells? — In PT there is a bottle neck analysis which might help you achieve it. Again, once you know the cells, manually fixing it might be less costly.

  12. Saketh

    I want to place decaps around the particular cell at the placement stage itself. Is it possible using ICC?
    If possible, pls tell me how to do it.

    1. krishna

      How come u know whether that particular cell require a decap?
      As EM/IR will be verified once the placement is done, then u can know the actual drop.
      These cells are known as preplaced cells, which were placed prior to placement.

    1. Sini Mukundan Post author

      When you enable multiple corners and modes while doing placement, the tool ensures that timing checks and timing optimizations are done for all modes/corners. You create an MCMM settings file and chose which modes to enable at various stages. The algorithm may differ for various EDA tools.

  13. Abhishek Patil

    Hello Sini,

    I have a query with std. Cell placement.
    Can we place a 10nm std. Cell in a 28nm environment?
    If their is a way to do so,please explain.


Leave a Reply

Your email address will not be published. Required fields are marked *