Physical Design Flow II:Placement

Physical Design Flow II:Placement

I. NetlistIn & Floorplan

After you have done floorplanning, i.e. created the core area, placed the macros, and decided the power network structure of your design, it is time to let the tool to do standard cell placement. The tool determines the location of each of the components (in digital design, standard cell instantiations) on the die. Various factors come into play, like the timing requirement of the system, the interconnect lengths and hence the connections between cells, power dissipation etc. The interconnect lengths depend on the placement solution used, and it is very important in determining the performance of the system as the geometries shrink.Placement also determines the routability of your design.

Placement does not just place the standard cells available in the synthesized netlist. It also optimizes the design, thereby removing any timing violations created due to the relative placement on die.

From a user perspective, these are the things important in placement.

  1. High fanout net synthesis High fanout nets other than clocks are synthesized at the placement stage. In logic synthesis, high fanout nets like reset, scan enable etc are not synthesized. You should verify that the SDC used for PnR should not have any `set_ideal_network` or `set_dont_touch` commands on these signals. Also, make sure you set an appropriate fanout limit for your library using the command `set_max_fanout`.

    e.g. `set_max_fanout 20 [current_design]`

    If a driver has too many loads, it will negatively affect the delay numbers and transitions values. After placement, look for any fanout violations in the timing report.

  2. Use Ideal clock You are going to synthesize your clock later in the design. So make sure you define the clocks as ideal. If you don't, HFN synthesis will be done on the clock. Clock constraints like skew or clock buffers are not used, and effectively your clock tree is messed up. In IC Compiler, you can use the following command to make sure clock is not propagated. `set_ideal_network [all_fanout -flat -clock_tree]`

  3. Control Congestion Congestion needs to be analysed after placement and the routing results depend on how congested your design is. Routing congestion may be localised. Some of the things that you can do to make sure routing is hassle free are:

    • Macro-padding: Macro padding or placement halos around the macros are placement blockages around the edge of the macros. This makes sure that no standard cells are placed near the pin outs of the macros, thereby giving extra breathing space for the macro pin connections to standard cells.
    • Maximum Utilization constraint: Some tools let you specify maximum core utilization numbers for specific regions. If any region has routing congestion, utilization there can be reduced, thus freeing up more area for routing. `set_congestion_options -max_util .6 -coordinate {837 114 1103 918}`
    • Placement blockages: The utilization constraint is not a hard rule, and if you want to specifically avoid placement in certain areas, use placement blockages.
  4. Scan chain reordering In a less complex design, you don't usually do scan reordering. However, sometimes it may become difficult to pass scan timing constraints once the placement is done. The scan flip flop placements may create lengthier routes if the consective flops in scan chain are placed far apart due to a functional requirement. In this case, the PnR tool can reconnect the scan chains, to make routing easier. A prerequisite for this option is a scan DEF for the tool to recognise the chains.

  5. TIE cells In your netlist, some unused inputs are tied to either VDD/VSS (or logic1/logic0). It is not recommended to connect a gate directly to the power network, so you can use TIEHI or TIELO cells if available in your library for the same. These are single pin cells which effectively ties the pin it connects high or low. After placement, dump out a netlist and serach for direct pin connections to the PG rails (other than power pins). There shouldn't be any if you are using tie cells.

    In IC Compiler, use the following commands to connect tie cells.

    set getTiePins [get_pins -of [get_nets -all -hier {VDD VSS}]]

    connect_tie_cells -objects $getTiePins -obj_type port_inst \ -tie_high_lib_cell TIEHIX1 -tie_low_lib_cell TIELOX1 -max_fanout 1

    TIE cells insertion flows differ slightly between tools, so go through the help.

  6. Spare cells Read this article on spare cell placement.

  7. Timing Your clock is not propagated, hence you have a zero skew at this point. Your timing reports should look pretty good. Make sure fanout constraints are met.

After placement, verify that all cells are placed on rows without any overlaps. You might find the following commands useful depending on your design. `check_legality report_placement_utilization report_level_shifters -verbose`

III. Clock Tree Synthesis IV. Routing V.Physical Verification