VLSI Pro

Physical Design Flow III:Clock Tree Synthesis

Physical Design Flow II:Placement

Physical Design Flow I : NetlistIn & Floorplanning

set_timing_derate

SVA : System Tasks & Functions

SVA : Introduction

SVA : Concurrent Assertions

Creating .lib file from verilog

ECO

Spare Cells

A glimpse on Metric Driven Verification Methodology

Sequential Equivalence Checking for high performance design

SPEF Files Explained

ICCompiler MCMM Flow - create_scenario

Reading ICC Timing Reports

Popular EDA Tools

Synopsys Design Constraints

Formal Verification - An Overview

Pages: P1 · P2 · P3 · P4