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Electrostatic Discharge
Intro
ESD Protection Device
Latent ESD Damage
General
Popular EDA Tools
Utility awk - Basics
Place & Route
Physical Design Flow
Intro
NetlistIn & Floorplanning
Placement
Clock Tree Synthesis
Routing
Physical Verification
ECO
Equivalency Checking Flow - Basics
PD Fundamentals
Multi-VT Cells
Noise Margins
Peak and Average Power
Physical Only Cells: Filler Cells
Physical Only Cells; Well Taps & Decap Cells
Integrated Clock Gating Cell
Power Dissipation: Leakage Power
Spare Cells
Technology LEF
Threshold Voltage
Body Effect
CMOS Latchup
PD Scripts
ICCompiler MCMM Flow - create_scenario
Clock Groups : set_clock_groups
Creating .lib file from verilog
SV Assertions
SVA : Introduction
SVA Basics: Bind
Concurrent Assertions
Properties
Basics
Types
Implication
Until Property
Sequences
Basics
Repetition Operators
Other Operators
Methods
Multiple Clock
System Verilog
Array-Querying System Functions
Array Reduction & Array Ordering Methods
SVA : System Tasks & Functions
System Verilog: Associative Arrays
System Verilog : Disable Fork & Wait Fork
System Verilog: Dynamic Arrays
System Verilog : Fork Join
System Verilog : Mailbox
System Verilog : Queues
System Verilog : Rand & Randc
System Verilog: Random Number System Functions
SV Constraint random value generation : Introduction
TCL Training
Uplevel
Upvar
Array as Argument
Timing Fundamentals
Synopsys Design Constraints
SPEF Files Explained
Multicycle paths between different clock domains
Reading ICC Timing Reports
set_timing_derate
set_clock_uncertainty
Multi Cycle Paths
STA - Setup and Hold Time Analysis
Standard Delay Format
Minimum Pulse Width Check
Insertion Delay & set_clock_latency
OCV & AOCV
Recovery and Removal Checks
Useful Skew
Clock Jitter
Clock Gating Checks
Common Path & Clock Reconvergence Pessimism Removal
Verification
A glimpse on Metric Driven Verification Methodology
Code Coverage Fundamentals
Formal Verification - An Overview
Sequential Equivalence Checking for high performance design
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hvt
Pages tagged hvt
PD Fundamentals
Threshold Voltage