SVA Basics: Bind

Binding SVA module to design can be done using system verilog bind statement. This is semantically equivalent to instantiation of SVA module. The bind directive can be specified in a module, interface or a compilation unit scope.

There are many ways binding can be done. Following section discusses these.

Normal Bind Binding fifo to fifosva assertion module can be done as follows

bind fifo fifosva fifosvainst (.clk(clki ),.rstn(rstni),.datai(datai),.datao(datao),.wr(wri),.rd(rdi))

Bind using Implicit port connections By using this method, port names need not be specified and all ports will be accessible to assertion module.

bind fifo fifosva fifosvainst(.\*);

Bind to a lower level module Hierarchy needs to be specified along with the bind statement.

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bind $root.vhdltop.sub1inst.sub2inst slavesvacheck slavebind(..)  //Design with vhdl top (in IFV tool)
bind vlogtop.sub1inst.sub2ins  slavesvacheck slavebind(..)  //vlog

Bind using different parameters/generic Passing parameter values in bind can be done in the following way.

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bind fifo fifosva #(.wordsize (8),.fifosize (32) ) 
                          fifosvainst (.clk(clki ),.rstn(rstni),
                                         .datai(datai),.datao(datao),
					 .wr(wri),.rd(rdi))

This helps to develop generic assertions.

Bind to a instance of a module If there are multiple instances of fifo module, and need to bind assertion to two of the instances (fifo1,fifo2). This can be done in the following way.

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bind fifo: fifo1, fifo2 fifosva fifosvainst2 (.clk(clki ),.rstn(rstni),.datai(datai),.datao(datao),.wr(wri),.rd(rdi))
bind fifo: fifo1 fifosva fifosvainst1 (.clk(clki ),.rstn(rstni),.datai(datai),.datao(datao),.wr(wri),.rd(rdi))  //binding to only fifo1 inst

So we can make the design untouched by developing assertions in a separate module and by using any of the above bind statements.