Minimum Pulse Width Check

Minimum pulse width checks are done to ensure that width of the clock signal is wide enough for the cell's internal operations to complete. i.e. to get a stable output you need to ensure that the clock signal at the clock pin of the flop is at least of a certain 'minimum' width.

If you need a formal definition of the term, it is the interval between the rising edge of the signal crossing 50% of VDD and the falling edge of the signal crossing 50% of VDD. If talking in terms of low signals, it is the the interval between falling edge of the signal crossing 50% of VDD and the rising edge of signal crossing 50% of VDD. Now you can see how the input pin transition or slew will affect the actual pulse width at any point. This is the reason why we use special CTS cells instead of regular buffers while creating a clock tree.

In ETS(or TEMPUS as the newest Cadence tool for STA is called), you will see a report like this:

   ---------------------------------------------------------------------------------------------------------------
                                    SEQUENTIAL CLOCK PULSE WIDTH
   ---------------------------------------------------------------------------------------------------------------
    Pin                                Required     Actual Pulse      Slack         Clock Name     View Name
                                      Pulse Width      Width
   ---------------------------------------------------------------------------------------------------------------
   clkctrlreg/CP (high)             0.3202          2.9731          2.6529       srcclk         funcmin

In this example, the clock period is 6ns with a duty cycle of 50%.i.e. Here, the clock signal at clkctrlreg/CP should be high at least for 0.3202ns (please note that the default time unit is ps in TEMPUS). The actual signal is high for 2.9731ns. Hence there is no minimum pulse width violation at the CP pin for srcclk.

Constraining the design

Now, let us see how you can specify this constraint for your design.

• Using .lib file
  Minimum pulse width depends on the technology node and the standard cell library design. You will have these modeled in your .lib file. Look for timingtype : min_pulse_width; in your liberty file. These will be defined for clock, reset and preset pins of a flop, or the enable pin of a latch.

      pin (CP) {
      clock : true;
      direction : input;
      max_transition : 2.5;
      capacitance : 0.00774191;

      timing () {
        related_pin : "CP";
        timing_type : minpulsewidth;
        rise_constraint (mpwconstraint) {
          index1 ("0.1, 0.6, 1.3, 1.9, 2.5");
          values ("0.131, 0.800, 1.596, 2.392, 3.066");
        }
        fall_constraint (mpwconstraint) {
          index1 ("0.1, 0.6, 1.3, 1.9, 2.5");
          values ( "0.361, 0.800, 1.596, 2.392, 3.066" );
        }
      }

The index1 is the transition at pin CP, and the last value in the table is the maxtransition of the pin. The values denote the minimum pulse width values for the pin transition specified.

• SDC command 'set_min_pulse_width'
  To set the minimum pulse width constraint, you can use the command set_min_pulse_width

set_min_pulse_width -high 3.0 \[allclocks\] set_min_pulse_width -low 2.0 \[allclocks\]

If neither high now low is specified the constraint applies to both high and low signal levels.

Reporting the violations

You can use in majority of STA tool, report_timing or a similar command.

report_timing -checktype pulsewidth

You can also use the command report_min_pulse_width in TEMPUS to report the pulse width values.