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Hamming Code
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Two Stage Synchonizers
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Multi-VT Cells
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Physical Only Cells: Filler Cells
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Integrated Clock Gating Cell
Power Dissipation: Leakage Power
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Technology LEF
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PD Scripts
ICCompiler MCMM Flow - create_scenario
Clock Groups : set_clock_groups
Creating .lib file from verilog
Semiconductor Physics
SV Assertions
SVA : Introduction
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SVA : System Tasks & Functions
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System Verilog: Dynamic Arrays
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System Verilog : Rand & Randc
System Verilog: Random Number System Functions
SV Constraint random value generation : Introduction
String Split in SV
TCL Training
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Upvar
Array as Argument
Timing Fundamentals
Synopsys Design Constraints
SPEF Files Explained
Multicycle paths between different clock domains
Reading ICC Timing Reports
set_timing_derate
set_clock_uncertainty
Multi Cycle Paths
STA - Setup and Hold Time Analysis
Standard Delay Format
Minimum Pulse Width Check
Insertion Delay & set_clock_latency
OCV & AOCV
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Useful Skew
Clock Jitter
Clock Gating Checks
Common Path & Clock Reconvergence Pessimism Removal
Verification
A glimpse on Metric Driven Verification Methodology
Code Coverage Fundamentals
Formal Verification - An Overview
Sequential Equivalence Checking for high performance design
Linting
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pd-scripts
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pd-scripts
Pages tagged pd-scripts
PD Scripts
Clock Groups : set_clock_groups
PD Scripts
Creating .lib file from verilog
PD Scripts
ICCompiler MCMM Flow - create_scenario